This invention relates to programmable logic array integrated circuits, and more particularly to improved organizations of the logic regions and interconnection conductors of such devices.
Several different "architectures" for programmable logic array devices are known. Pedersen et al. U.S. Pat. No. 5,260,610, for example, shows programmable logic array devices in which blocks of programmable logic regions are disposed on the device in a two-dimensional array of intersecting rows and columns of such blocks. Each block includes a plurality of logic regions and a plurality of local feedback conductors for making the output of each logic region in the block selectively available as an input to any logic region in that block. Global horizontal conductors are associated with each row of blocks for conveying signals between the blocks in that row. Global vertical conductors are associated with each column of blocks for conveying signals from row to row.
The Pedersen et al. architecture has many advantages such as relatively high-speed signal conduction due to the continuous, long, global horizontal and vertical conductors. In some applications, however, this architecture may have certain disadvantages. Grouping logic regions into discrete blocks means that a long global conductor must be used whenever a connection is required between logic regions that are not in the same block. Even if the logic regions requiring interconnection are in immediately adjacent blocks, a global conductor (which is much longer than the required interconnection) must be used to make the interconnection. This is wasteful of interconnection resources.
Another possible disadvantage of the Pedersen et al. architecture may be that each global horizontal conductor has many switchable taps along its length because the logic region inputs are fed directly from the global horizontal conductors. These taps can cause significant loading of the global horizontal conductor circuits, which may tend to increase the power required to drive those circuits, and which may also tend to make those circuits not as fast as they would be with fewer programmable taps.
An architecture which addresses some of the possible disadvantages of the Pedersen et al. architecture is shown in Cliff et al. U.S. Pat. No. 5,260,611. The Cliff et al. architecture reduces the number of switchable taps on the global horizontal conductors by tapping those conductors to block input conductors associated with each block, the number of taps to the block input conductors and the number of block input conductors associated with each block being less than the total number of inputs to the logic regions in the block. Each block input conductor is programmably selectively connectable to any logic region in the block.
While the Cliff et al. architecture offers some possible improvements over the Pedersen et al. architecture, it does not improve on the Pedersen et al. architecture in other respects. The Cliff et al. architecture still requires an entire global horizontal or vertical conductor to be used for even relatively short interconnections between blocks. Moreover, if a global horizontal conductor must feed logic regions that happen to be in two adjacent blocks, two block input conductors (one in each of the two adjacent blocks) must be used to get that signal into the two blocks.
A different type of architecture is shown in Freeman U.S. Pat. No. Reissue 34,363. In this architecture short interconnection conductors adjacent to each logic region are programmably interconnectable to one another to make interconnections between any but the most closely adjacent logic regions. A possible disadvantage of this architecture is that large numbers of short conductor segments must be "pieced together" to make long interconnections, which tend to be relatively slow due to the large number of programmable switches that the interconnection signal must pass through. More recent commercial products of Freeman's assignee, Xilinx, Inc., have added longer, uninterrupted conductors, and also uninterrupted conductors between adjacent logic regions (see, for example, Carter U.S. Pat. No. 4,642,487). However, these products still rely heavily on piecing together many relatively short interconnection conductors to make certain kinds of interconnections.
An architecture which relies on piecing together different numbers of interconnection conductors to produce interconnections of different lengths greatly exacerbates the problem of longer signal paths having greater signal transmission delays. This is so because in such architectures longer interconnections tend to be made up of more pieced together segments than shorter interconnections, and each such piecing together adds significant signal transmission delay. Different transmission times for different signal paths make it more difficult to maintain synchronization among various signals and may necessitate designing the chip to operate at a slower overall speed. In other words, the speed of the slowest signal transmission path may dictate the design speed of the overall chip.
Other architectures which rely heavily on piecing together many relatively short conductor segments are shown in Elgamal et al. U.S. Pat. No. 4,758,745, El Gamal et al., "An Architecture for Electrically Configurable Gate Arrays"IEEE Journal of Solid-State Circuits, Vol. 24, No. 2, pp. 394-98, April 1989, and El-Ayat et al., "A CMOS Electrically Configurable Gate Array"IEEE Journal of Solid-State Circuits, Vol. 24, No. 3, pp. 752-62, June 1989. The devices shown in these references are programmable one time only (i.e., they are not reprogrammable).
Although the present invention is applicable to both one-time-programmable and reprogrammable devices, the invention is especially beneficial in connection with reprogrammable devices. Reprogrammable connections tend to be larger (e.g., than the one-time-programmable anti-fuses shown in the above-mentioned Elgamal et al. patent ). This increases signal delay and circuit loading associated with reprogrammable connections. The larger size of reprogrammable connections also makes it important to reduce the number of these connections that are used. For example, if all interconnection regions in an integrated circuit device are fully populated with reprogrammable connections (i.e., if every input to each such interconnection region is connectable to every output of that region), the device tends to become too large. For all of these reasons, reprogrammability strongly pushes the design in the direction of economizing on the number of reprogrammable interconnections that are provided. As interconnection regions are made only partly populated in response to this pressure, it becomes even more important to use sophisticated techniques to ensure maximum routability of signals through the device (i.e., to provide interconnection resources with maximum flexibility and usability so that the maximum number of different interconnection patterns that are possible with signal blockage not occurring prematurely or significantly before substantially all logic regions of the device have been put to use). Thus, while the goals of this invention are of interest regardless of the technology used to implement the integrated circuit device, considerations such as the larger size, loading, and delay of typical reprogrammable interconnection elements makes the invention especially important in connection with reprogrammable devices.
In view of the foregoing, it is an object of this invention to provide improved organizations for the logic regions and interconnection conductors of programmable logic array integrated circuit devices.
It is another object of this invention to provide more options for making connections to and/or interconnections between relatively closely adjacent logic regions so as to make more efficient use of the conductors that make such connections and/or to reduce the need to use relatively long global conductors to make such interconnections, but without resorting to the undesirable expedient of piecing together many relatively short conductors when longer interconnection are required.